Chaotic oscillator-based random number generation

A circuit, comprising:

• a relaxation oscillator to receive a direct current (DC) input voltage as input, and having a capacitance in parallel with a negative differential resistance (NDR) component to provide an oscillating output voltage, where the NDR component receives an alternating current (AC) bias and the capacitance has a value such that the oscillating output voltage has a chaotic period;
• and
• a random number generator to generate random numbers using samples of the output voltage;
• wherein the relaxation oscillator is formed on a semiconductor substrate, and wherein the NDR component comprises a metal-oxide-metal device formed on the semiconductor substrate.

A circuit, comprising:

• a direct current (DC) bias source;
• a resistance in series with the DC bias source;
• a negative differential resistance (NDR) device in series with the resistance;
• an alternating current (AC) bias source in series with the NDR device;
• a capacitance in parallel with the NDR device;
• and
• a random number generator to generate random numbers using samples of a voltage across the capacitance;
• wherein the circuit is formed on a semiconductor device, and wherein the NDR device comprises a metal-oxide-metal device formed on the semiconductor device.

A circuit, comprising:

• a negative differential resistance (NDR) device to receive an alternating current (AC) bias;
• a capacitance in parallel with the NDR device, the capacitance having a value such that, in response to a direct current (DC) bias applied to the NDR device and the capacitance, a voltage across the capacitance oscillates with a chaotic period;
• and
• a random number generator to generate random numbers using samples of the voltage across the capacitance;
• wherein the capacitance is an adjustable capacitor.