Level shift circuit and semiconductor device

A level shift circuit comprising:

• a conversion circuit that includes a transistor, which receives an input signal, and converts an amplitude of the input signal and;
• a detection circuit that includes a replica transistor which is a replicate of the transistor and detects whether the replica transistor becomes activated or inactivated in response to a voltage level of the input signal and outputs a detection signal;
• and
• a voltage output circuit coupled to the conversion circuit and the detection circuit, wherein the voltage output circuit applies body bias to a back gate of the transistor so that the replica transistor becomes activated in response to the detection signal from the detection circuit indicating that the replica transistor is inactivated.

A semiconductor device comprising:

• a first circuit that operates on a first voltage;
• a second circuit that operates on a second voltage, which is greater than the first voltage;
• and
• a level shift circuit coupled to the first and second circuit to convert an input signal having a signal level of the first voltage received from the first circuit into a signal having a signal level of the second voltage to provide the converted signal to the second circuit, wherein the level shift circuit includes a level conversion unit, and the level conversion unit includes first and second MOS transistors of a first conductivity type and third and fourth MOS transistors of a second conductivity type, which differs from the first conductivity type and of which switching is controlled in a complementary manner in accordance with the input signal, the third and fourth MOS transistors include drains supplied with the second voltage via the first and second MOS transistors, respectively;
• and
• a control unit coupled to the level conversion unit, wherein the control unit, when receiving a detection signal indicating a decrease in the first voltage, controls a voltage value of a body bias applied to a back gate of the third and fourth MOS transistors to decrease a threshold voltage of the third and fourth MOS transistors.