Methods and delay circuits for generating a plurality of delays in delay lines

A delay circuit comprising:

• a delay line set comprising a plurality of delay lines, each of the plurality of delay lines configured to provide a plurality of delays, the delay line set comprising an input terminal configured to receive a clock signal and an output terminal;
• a constant delay block coupled with the input terminal of the delay line set, the constant delay block configured to delay the clock signal by an intrinsic delay of the plurality of delay lines;
• a control circuit coupled with the delay line set, the control circuit configured to determine a first number of delay steps corresponding to the intrinsic delay of each of the plurality of delay lines and determine a second number of delay steps based on the first number of delay steps so as to provide the plurality of delays through each of the plurality of delay lines, the intrinsic delay being a minimum delay contributed by each of the plurality of delay lines;
• and
• a configuration circuit coupled with the constant delay block and the delay line set, the configuration circuit configured to configure each of the plurality of delay lines to generate the plurality of delays based on the number of delay steps and thereby enable provision of the plurality of delays through each of the plurality of delay lines.

A delay circuit comprising:

• a delay line set comprising a plurality of delay lines, each of the plurality of delay lines configured to provide a plurality of delays, the delay line set comprising an input terminal configured to receive a clock signal and an output terminal configured to provide a delayed signal;
• a control circuit coupled with the delay line set, the control circuit configured to determine the first number of delay steps corresponding to an intrinsic delay of the delay line set and determine the second number of delay steps based on the first number of delay steps so as to provide the plurality of delays through each of the plurality of delay lines, the intrinsic delay being a minimum delay contributed by each of the plurality of delay lines;
• and
• a configuration circuit coupled with the delay line set, the configuration circuit configured to configure each of the plurality of delay lines to generate the plurality of delays based on the second number of steps and thereby enable provision of the plurality of delays through each of the plurality of delay lines.