Double edge triggered flip flop
AssigneeFreescale Semiconductor, Inc.
InventorRavindraraj Ramaraju
Life of this patent
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Abstract
A dual edge triggered flip flop circuit uses clock signals that are delayed from a first clock signal and from one another by respective intervals. A first set of the plurality of clock signals are used to operate a first latch circuit to allow first data to be conducted to a storage element for a period of time after a rising edge of a first clock signal. The clock signals are further used to operate a second latch circuit to allow second data to be conducted to the storage element for a period of time after a falling edge of the first clock signal.
Claims14
A dual edge triggered flip flop circuit, comprising:
- a single storage element;
- a first latch circuit and a second latch circuit coupled to alternate input to the single storage element between a first feedback path and a second feedback path on rising and falling edges of a first clock signal;
- and
- a clock signal generator configured to receive the first clock signal and to output a plurality of clock signals including a first inverted clock signal, a second clock signal, and a second inverted clock signal, wherein the plurality of clock signals are delayed from one another and from the first clock signal by respective specified intervals;
- and
- wherein:
- the first latch circuit is in a conducting state and the second latch circuit is in a non-conducting state for a first window of time at the rising edge of the first clock signal;
- and
- the second latch circuit is in a conducting state and the first latch circuit is in a non-conducting state for a second window of time at the falling edge of the first clock signal.
A dual edge triggered flip flop circuit comprising:
- a storage element shared between a first latch circuit and a second latch circuit;
- a clock signal generator configured to receive a first clock signal and to output a plurality of clock signals including a first inverted clock signal, a second clock signal, and a second inverted clock signal, wherein the plurality of clock signals are delayed from one another and from the first clock signal by respective specified intervals;
- the first latch circuit includes a first transmission gate controlled by the second clock signal and the second inverted clock signal to allow input of first data to the storage element during a period of time after a rising edge of the first clock signal;
- and
- the second latch circuit includes a first transmission gate controlled by the second clock signal and the second inverted clock signal in polarity opposite to the first transmission gate of the first latch circuit to allow input of second data to the storage element during a period of time after the falling edge of the first clock signal;
- wherein the first latch circuit further includes a second transmission gate and a third transmission gate, the second and third transmission gates of the first latch circuit comprise a P-MOS switch controlled by the first inverted clock signal and a N-MOS switch controlled by the second clock signal.
Dependencies are inferred from the claim text.