US 8,542,044 B2 · Semiconductor integrated circuit and method for driving the same

Abstract

A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

Claims20

Dependent claims

A semiconductor integrated circuit comprising:

a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed;
and
an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

A method for driving a semiconductor integrated circuit which includes a DLL configured to generate a DLL clock signal by delaying a source clock by a first delay time for obtaining a lock and an update period controller configured to control an update period of the DLL, the method comprising:

generating, by the DLL, the DLL clock signal by delaying a source clock signal by the first delay time, wherein the first delay time is variably controlled;
controlling, by the update period controller, the update period based on a second delay time that occurs in a loop path of the DLL in a state in which the generating of the DLL dock signal is completed;
and
performing, by the DLL, an update in response to the controlled update period.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

13/334,241Filed 22 Dec 2011

Priority

KR 10-2011-010758720 Oct 2011

Published

US 2013/0099838 A125 Apr 2013

Granted

24 Sep 2013

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…
G11C 29/023
Detection or location of defective auxiliary circuits, e.g. defective refresh counters: in clock generator or timing circuitry
H03L 7/0816
And where no voltage or current controlled oscillator is used: the controlled phase shifter and the frequency- or phase-detection arrangement…

Semiconductor integrated circuit and method for driving the same

Life of this patent

Semiconductor integrated circuit and method for driving the same

Life of this patent

Abstract

Claims20