Reconfigurable divider circuits with hybrid structure
AssigneeIntegrated Device Technology, Inc.
InventorJustin O'Day
Life of this patent
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Abstract
An integrated circuit includes a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal and a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal. The integrated circuit further includes a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.
Claims19
An integrated circuit comprising:
- a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;
- a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal;
- and
- a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.
An integrated circuit comprising:
- a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;
- a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal, wherein the second variable divider circuit comprises:
- a plurality of groups of cascade-connected flip-flops having clock inputs that receive the clock signal;
- a plurality of first multiplexer circuits, respective ones of which have inputs coupled to outputs of flip-flops of respective ones of the groups of flip-flops and configured to selectively pass signals therefrom to a data input of another one of the groups of flip-flops;
- a second multiplexer circuit coupled to an output of a last one of the groups of flip-flops and configured to selectively pass signals therefrom to output the second divided clock signal;
- and
- a feedback circuit having an input coupled to the second multiplexer circuit and an output coupled to a first one of the groups of flip-flops;
- and
- a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input.
An integrated circuit comprising:
- a first variable divider circuit configured to receive a clock signal and to apply a lower range of integer division factors thereto responsive to a first control input to generate a first divided clock signal;
- a second variable divider circuit configured to receive the clock signal and to apply an upper range of integer division factors thereto responsive to a second control input to generate a second divided clock signal;
- and
- a multiplexer circuit configured to selectively pass the first and second divided clock signals responsive to a third control input, wherein the second variable divider circuit provides less inter-flip-flop delay than the first variable divider circuit.
Dependencies are inferred from the claim text.