Three-dimensional (3D) stacked integrated circuit testing
AssigneeInternational Business Machines Corporation
InventorsChen-Yong Cher, Eren Kursun, Gary W. Maier, Raphael Peter Robertazzi
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AssigneeInternational Business Machines Corporation
InventorsChen-Yong Cher, Eren Kursun, Gary W. Maier, Raphael Peter Robertazzi
Estimating the term…
Testing of a three-dimensional (3D) integrated circuit includes defining a first group of parts by a region and/or layer on the 3D integrated circuit. The testing further includes applying a first intensity of stress test conditions to the first group of parts. The testing also includes defining a second group of parts by a region and/or layer on the 3D integrated circuit that is different from the first group of parts. The testing further includes and applying a second intensity of stress test conditions to the second group of parts. The second intensity of stress test conditions is greater than the first intensity and is determined by sensitivities identified for each of the first and second group of parts. A determination is made whether the 3D integrated circuit passed the testing based upon results of application of the first and second intensities of stress test conditions.
A method of testing a three-dimensional (3D) integrated circuit, the method comprising:
A system of testing a three-dimensional (3D) integrated circuit, the system comprising:
Dependencies are inferred from the claim text.