Back to results
US 8,541,886 B2Granted
Integrated circuit packaging system with via and method of manufacture thereof
AssigneeSTATS ChipPAC, Ltd.
InventorChee Keong Chin
Life of this patent
Estimating the term…
Abstract
A method of manufacture of an integrated circuit packaging system includes: providing a stacking carrier having a cavity; placing a base integrated circuit in the cavity, the base integrated circuit having a base interconnect facing the cavity; mounting a stack integrated circuit to the base integrated circuit; and picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier.
Claims11
A method of manufacture of an integrated circuit packaging system comprising:
- providing a stacking carrier having a cavity and a support step in the cavity, wherein providing the stacking carrier includes providing the stacking carrier having a compliant layer in the cavity;
- placing a base integrated circuit in the cavity, the base integrated circuit having a peripheral region and a base interconnect facing the cavity, the peripheral region on the support step, wherein placing the base integrated circuit in the cavity includes placing the base interconnect on the compliant layer;
- mounting a stack integrated circuit to the base integrated circuit;
- and
- picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier wherein the base integrated circuit comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step.
2 more elements
A method of manufacture of an integrated circuit packaging system comprising:
- providing a stacking carrier having a cavity, a cavity bottom, and a support step in the cavity, the cavity bottom below the support step, wherein providing the stacking carrier includes providing the stacking carrier having a compliant layer on the cavity bottom;
- placing a base integrated circuit in the cavity, the base integrated circuit having a peripheral region, a gap, a base interconnect, and a through via with the base interconnect facing the cavity, the peripheral region on the support step, and the gap between the base interconnect and the cavity bottom, wherein placing the base integrated circuit in the cavity includes placing the base interconnect on the compliant layer;
- mounting a stack integrated circuit to the base integrated circuit, the stack integrated circuit connected to the through via;
- and
- picking the stack integrated circuit mounted to the base integrated circuit out of the stacking carrier wherein the base integrated circuit comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step.
2 more elements
An integrated circuit packaging system comprising:
- a base integrated circuit having a peripheral region and a base interconnect, the peripheral region having an impression mark characteristic of the base integrated circuit being placed on a support step in a cavity of a stacking carrier, wherein the base integrated circuit includes the base interconnect comprises the peripheral region having an impression mark characteristic of the base integrated circuit being placed on the support step, and having a tacky residue characteristic of a compliant layer of the stacking carrier removed from the base interconnect;
- and
- a stack integrated circuit mounted to the base integrated circuit, wherein the base base integrated circuit includes a through via, and wherein the stack integrated circuit is connected to the through via.
Dependencies are inferred from the claim text.