High-k transistors with low threshold voltage

A semiconductor structure comprising:

• a plurality of p-type and n-type transistor devices formed over a substrate, each of the transistor devices comprising a high-k dielectric layer over the semiconductor substrate, and a gate layer over the high-k dielectric layer;
• an insulating layer disposed over the gate layer of only the n-type transistor devices;
• and
• a metal layer formed over the insulating layer and the gate layer of the p-type transistor devices so as to electrically connect the plurality of p-type devices to one another;
• wherein the gate layer of only the p-type transistor devices is configured to receive a negative electrical bias during anneal.