Integrated circuit memory devices having vertical transistor arrays therein and methods of forming same

A semiconductor memory device comprising:

• a ground selection structure and a string selection structure being apart from each other;
• at least one memory structure between the ground and string selection structures, the memory structure comprising a plurality of word lines stacked sequentially;
• at least one semiconductor pattern crossing the word lines to connect the ground selection structure to the string selection structure and covering a top surface and sidewall of the memory structure;
• and
• a substrate disposed under the ground and string selection structures and the memory structure;
• wherein the ground and string selection structures comprise MOSFETs using the substrate as channel regions therein, and
• wherein the memory structure comprises MOSFETs, which are sequentially stacked over the substrate and use the semiconductor pattern as channel regions therein.

A non-volatile memory device, comprising:

• a NAND-type string of non-volatile memory cells including:
• at least a first vertically-stacked array of charge trap memory cells on a semiconductor substrate, said first vertically-stacked array of charge trap memory cells comprising a semiconductor layer that covers first and second opposing sidewalls thereof, said semiconductor layer containing channel regions of the first vertically-stacked array of charge trap memory cells therein;
• a string select transistor on a first side of the first vertically-stacked array of charge trap memory cells, said string select transistor having a first source/drain terminal electrically connected to the semiconductor layer;
• and
• a ground select transistor on a second side of the first vertically stacked array of charge trap memory cells, said string select and ground select transistors having respective channel regions in the semiconductor substrate.