US 8,541,830 B1 · Nonvolatile semiconductor memory device and method for manufacturing the same

Abstract

A nonvolatile semiconductor memory device according to an embodiment includes a plurality of cell array layers, each cell array layer including: a plurality of semiconductor layers that extends in a first direction; gate insulating layers; a plurality of floating gates arranged in the first direction; inter-gate insulating layers; and a plurality of control gates that extends in a second direction intersecting semiconductor layers, and faces the floating gates via the inter-gate insulating layers, in which, in the cell array layers adjacent each other in a stacking direction, the control gates of a lower cell array layer and the control gates of the an upper cell array layer are intersecting each other, and the floating gates within the lower cell array layer and the semiconductor layers within the upper cell array layer are aligned in position with each other.

Claims20

Dependent claims

A nonvolatile semiconductor memory device comprising a plurality of memory cell array layers being stacked, each memory cell array layer including:

a plurality of semiconductor layers, each extending in a first direction and being in parallel to each other;
gate insulating layers formed on the semiconductor layers;
a plurality of floating gates formed on the gate insulating layers and arranged in the first direction;
inter-gate insulating layers adjacent to the floating gates;
and
a plurality of control gates that face the floating gates via the inter-gate insulating layers at both sides of the floating gates in the first direction and that extend in a second direction intersecting the first direction,
in the cell array layers adjacent to each other in a stacking direction, the control gates of the cell array layer in a lower cell array layer and the control gates of the cell array layer in an upper cell array layer intersecting each other, the floating gates in the lower cell array layer and the semiconductor layers on the floating gates being aligned in position with each other.

4 more elements

A nonvolatile semiconductor memory device comprising a first cell array layer and a second cell array layer stacked on the first cell array layer,

the first cell array layer being configured by arranging first memory cell units in a second direction intersecting a first direction, the first memory cell unit including a plurality of first memory cells connected in series to each other in the first direction and first select gate transistors connected to both ends of the connected first memory cells;
the plurality of first memory cells having a configuration in which each memory cell includes a first semiconductor layer extending in the first direction, a first gate insulating layer formed on the first semiconductor layer, a plurality of first floating gates provided on the first gate insulating layer and arranged along the first direction, and first control gates formed on both sides in the first direction of the first floating gate via the inter-gate insulating films;
the first control gates extending in the second direction and being commonly provided for the plurality of the first memory units arranged in the second direction;
the second cell array layer being configured by arranging second memory cell units in the second direction, the second memory cell unit including a plurality of second memory cells connected in series to each other in the second direction and second select gate transistors connected to both ends of the connected second memory cells;
the plurality of second memory cells having a configuration in which each memory cell includes a second semiconductor layer extending in the second direction, a second gate insulating layer formed on the second semiconductor layer, a plurality of second floating gates provided on the second gate insulating layer and arranged along the second direction, and second control gates formed on both sides in the second direction of the second floating gate via inter-gate insulating films;
the second control gates extending in the first direction, and being commonly provided for the plurality of the second memory units arranged in the first direction;
and
the first floating gate and the second semiconductor layer being aligned in position with each other.

5 more elements

A method for manufacturing a nonvolatile semiconductor memory device, comprising:

sequentially stacking a first semiconductor layer, a first gate insulating layer, a first floating gate layer, and a first inter-layer insulating layer;
dividing an obtained stacked body into a plurality of stacked bodies separated from each other in a second direction intersecting a first direction by a trench extending in the first direction;
filling the trench extending in the first direction with a second inter-layer insulating layer;
sequentially stacking a second semiconductor layer, a second gate insulating layer, a second floating gate layer, and a third inter-layer insulating layer on the stacked body and the second inter-layer insulating layer;
and
dividing the obtained stacked body ranging from the third inter-layer insulating layer to an upper surface of the first gate insulating layer into a plurality of stacked bodies separated from each other in the first direction by a trench extending in the second direction.

3 more elements

Dependencies are inferred from the claim text.

Nonvolatile semiconductor memory device and method for manufacturing the same

Life of this patent

Nonvolatile semiconductor memory device and method for manufacturing the same

Life of this patent

Abstract

Claims20