Nonvolatile semiconductor memory and fabrication method for the same

A nonvolatile semiconductor memory comprising

• a substrate;
• a cell array region that is disposed on the substrate including a memory cell transistor, which comprises;
• first source and drain regions,
• a tunneling insulating film formed on a semiconductor region between the first source and drain regions,
• an electric storage layer formed on the tunneling insulating film,
• a first insulating film formed on the electric storage layer,
• a first control gate electrode layer formed on the first insulating film, and
• a first metallic silicide film electrically connected to the first control gate electrode layer;
• a high voltage circuit region that is disposed on a different area of the substrate from the cell array region and comprises:
• a high voltage transistor, which comprises second source and drain regions,
• a high voltage gate insulating film formed on a semiconductor region between the second source and drain regions,
• a high voltage gate electrode layer formed on the high voltage gate insulating film, and
• a second metallic silicide film electrically connected to the high voltage gate electrode layer;
• a low voltage circuit region that is disposed on a different area of the substrate from the cell array region and the high voltage circuit region, and comprises:
• a low voltage transistor that comprises third source and drain regions,
• a low voltage gate insulating film formed on a semiconductor region between the third source and drain regions,
• a low voltage gate electrode layer formed on the low voltage gate insulating film, and
• a third metallic silicide film electrically connected to the low voltage gate electrode layer;
• a liner insulating film disposed on the first source and drain regions, the second source and drain regions, the third source and drain regions, side surfaces of the memory cell transistor, the high voltage transistor, and the low voltage transistor;
• and
• a barrier insulating film disposed above the memory cell transistor, the high voltage transistor, and the low voltage transistor, and contacting an upper surface of the first to third metallic silicide films, and contacting the liner insulating film at edges of the memory cell transistor, the high voltage transistor, and the low voltage transistor;
• wherein the thickness of the high voltage gate insulating film is greater than thickness of the tunneling insulating film and the low voltage gate insulating film, and an upper surface of the high voltage gate insulating film and an upper surface of the tunneling insulating film and an upper surface of the low voltage gate insulating film have substantially the same height.