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US 8,541,827 B2Granted
Semiconductor memory device including multi-layer gate structure
AssigneeKabushiki Kaisha Toshiba
InventorToshitake Yaegashi
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Abstract
A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.
Claims12
A semiconductor memory device comprising:
- (a) a first transistor formed on an upper surface of a substrate;
- (b) a first stepped portion disposed adjacent to one side of a gate of the first transistor such that the first stepped portion forms a cavity in the upper surface of said substrate in a first direction;
- (c) a first contact plug formed in a region of the first stepped portion, the first contact plug being partially in contact with the first stepped portion;
- and
- (d) an insulating film in a trench in a second direction crossing to the first direction,
- wherein an upper surface of the insulating film is higher than the upper surface of said substrate in the cavity.
3 more elements
Dependencies are inferred from the claim text.