Memory array structure and method for forming the same

A method for forming a memory array structure, comprising steps of:

• providing a substrate;
• forming a bit line layer and a channel layer on the substrate sequentially;
• forming a plurality of second trenches in a second direction, wherein a bottom of each second trench is lower than a surface of the substrate;
• forming a first isolation layer in each second trench;
• forming a plurality of first trenches in a first direction, wherein a bottom of each first trench is higher than the surface of the substrate but lower than a surface of the bit line layer;
• forming a gate structure which includes a gate dielectric and a gate electrode, and a word line in each first trench to obtain a patterned wafer;
• forming a second mask layer on the patterned wafer and forming a plurality of third trenches in the second mask layer in the first direction, wherein a first portion of each third trench is located on the channel layer and a second portion of each third trench is located on a part of the gate electrodes and one word line;
• forming a body line in each third trench for providing a substrate contact to the channel layer;
• etching the second mask layer to form a side wall on each side of each body line and expose a part of the channel layer;
• forming a source region or a drain region in an upper portion of each exposed part of the channel layer so that a lower portion of each exposed part of the channel layer is a corresponding drain region or a corresponding source region to form a plurality of vertical transistors, wherein each vertical transistor comprises a semiconductor pillar, a gate structure which includes a gate dielectric and a gate electrode and is formed on a side wall of the semiconductor pillar, a source region and a drain region, and a vertical channel region formed between the source region and the drain region;
• and
• forming a data storage device contact on each source region or each drain region for connecting a data storage device with each vertical transistor via each data storage device contact.