Hybrid CMOS technology with nanowire devices and double gated planar devices

An integrated circuit comprising a plurality of field effect transistor (FET) devices disposed over a common substrate, said plurality of FET devices comprising:

• a first source region comprising a first semiconductor layer disposed on a second semiconductor layer, the first source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a first drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the first drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a plurality of nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members are formed from the first semiconductor layer, and have opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
• a second source region comprising the first semiconductor layer disposed on the second semiconductor layer, the second source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a second drain region comprising the first semiconductor layer disposed on the second semiconductor layer, the second drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a single channel member suspended by the second source region and the second drain region, where the single channel member is formed from the first semiconductor layer, and has opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
• and
• a first gate formed around at least a portion of the nanowire channel members and a second gate formed around at least a portion of the single channel member.

An integrated circuit comprising:

• a plurality of field effect transistor (FET) devices disposed over a common silicon on insulator (SOI) substrate comprising a layer of buried oxide (BOX) having an overlying layer of silicon, said plurality of FET devices comprising:
• a first source region comprising a first semiconductor layer disposed on top of a second semiconductor layer that is disposed on top of the layer of silicon, the first source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a first drain region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the first drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a plurality of nanowire channel members suspended by the first source region and the first drain region, where the nanowire channel members are formed from the first semiconductor layer and have opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes;
• a second source region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the second source region having a surface parallel to {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a second drain region comprising the first semiconductor layer disposed on top of the second semiconductor layer that is disposed on top of the layer of silicon, the second drain region having a face parallel to the {110} crystalline planes and opposing sidewall surfaces parallel to the {110} crystalline planes;
• a single channel member suspended by the second source region and the second drain region, where the single channel member is formed from the first semiconductor layer and has opposing sidewall surfaces parallel to {100} crystalline planes and opposing faces parallel to the {110} crystalline planes, where a width of the single channel member is at least several times a width of a single nanowire member;
• and
• a first gate formed around at least a portion of the nanowire channel members and a second gate formed around at least a portion of the single channel member.