Solid-state image sensor
AssigneesShimadzu Corporation, Tohoku University
InventorsShigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
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AssigneesShimadzu Corporation, Tohoku University
InventorsShigetoshi Sugawa, Yasushi Kondo, Hideki Tominaga
Estimating the term…
A pixel output line is provided for each of the pixels two-dimensionally arrayed in a pixel area. The pixel output lines are extended to a memory area, and a memory unit is connected to each of those lines. The memory unit includes a writing-side transistor, a reading-side transistor and a plurality of memory sections for holding signals for 104 image frames. A photocharge storage operation is simultaneously performed at all the pixels, and the thereby produced signals are outputted to the pixel output lines. In the memory unit, with the writing-side transistor in the ON state, the sampling transistor of a different memory section is sequentially turned on for each exposure cycle so as to sequentially hold a signal in the capacitor of each memory section. After a burst imaging operation is completed, all the pixel signals are sequentially read. Unlike CCDs, the present device does not simultaneously drive all gate loads, so that it can be driven at high speeds with low power consumption. Thus, the burst imaging can be performed at higher speeds than ever before.
A solid-state image sensor, which is characterized by comprising in that the image sensor comprises:
A solid-state image sensor comprising:
A solid-state image sensor,
Dependencies are inferred from the claim text.