US 8,541,293 B2Granted

Method of controlled lateral etching

AssigneeInstitute of Microelectronics, Academy of Sciences

InventorsHuilong Zhu, Zhijiong Luo, Haizhou Yin

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Abstract

A method of controlled lateral etching is disclosed. In one embodiment, the method may comprise: forming on a first material layer, which comprises a protruding structure, a second material layer; forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure; forming a third material layer on surfaces of the second material layer and the spacers; forming on the third material layer a mask layer which extends in a direction lateral to a surface of the first material layer; and laterally etching portions of the respective layers arranged on the vertical surfaces of the protruding structure.

Claims11

Dependent claims

A method of controlled lateral etching, comprising:

forming a second material layer on a first material layer having a protruding structure, the second material layer comprising laterally extending portions and vertically extending portions;
forming spacers on outer surfaces of the second material layer opposite to vertical surfaces of the protruding structure;
forming a third material layer on surfaces of the second material layer and the spacers, the third material layer comprising laterally extending portions and vertically extending portions;
forming a mask layer, which extends in a direction lateral to a surface of the first material layer, on the third material layer;
and
laterally etching the vertically extending portions of the third material layer, the spacers, and the vertically extending portions of the second material layer sequentially, to leave a functional layer composed of the laterally extending portions of the second material layer and the laterally extending portions of the third material layer on the first material layer.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/509,604Filed 23 Nov 2011
Priority: CN 2011 1 028136421 Sep 2011
Published: US 2013/0072023 A121 Mar 2013
Granted: 24 Sep 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 84/0158
The components including insulated gates, e.g. IGFETs: the components including FinFETs
H10D 84/0193
The components including complementary IGFETs, e.g. CMOS devices: the components including FinFETs

Family

US 2013/0072023 A1Pre-grant publication · published 21 Mar 2013
US 8,541,293 B2This patent

From the US filing history. Foreign family members aren’t listed.

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