Replacement gate process flow for highly scaled semiconductor devices

A method, comprising:

• forming sacrificial gate structures for both a PFET transistor and an NFET transistor above a P-active region and an N-active region, respectively, of a semiconducting substrate;
• forming at least one sidewall spacer proximate each of said sacrificial gate structures of each of said PFET and NFET transistors;
• forming a first layer of insulating material adjacent said sidewall spacer for each of said PFET and NFET transistors;
• removing said sacrificial gate structures of said PFET transistor and said NFET transistor to thereby define a gate cavity for each of said PFET transistor and said NFET transistor;
• forming a replacement P-type gate structure in said gate cavity of said PFET transistor and a replacement N-type gate structure in said gate cavity of said NFET transistor;
• after forming said replacement P-type and N-type gate structures for both of said PFET and NFET transistors, respectively, forming a second layer of insulating material above said first layer of insulating material;
• after forming said replacement P-type and N-type gate structures, forming a plurality of P-contact openings and a plurality of N-contact openings in said first and second layers of insulating material, wherein said P-contact openings expose portions of said P-active region and said N-contact openings expose portions of said N-active region;
• forming a masking layer that covers said exposed portions of said N-active region;
• with said masking layer in place, performing at least one etching process though said P-contact openings in said first and second layers of insulating material to define a plurality of source/drain cavities in said P-active region proximate said P-type replacement gate structure of said PFET transistor;
• and
• with said masking layer in place, performing at least one epitaxial deposition process through said P-contact openings to form source/drain regions comprised of a semiconducting material in at least said source/drain cavities of said PFET transistor.