Method for manufacturing a semiconductor device having high-voltage and low-voltage transistors
AssigneeSeiko Instruments Inc.
InventorYuichiro Kitajima
Life of this patent
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Abstract
By covering ends of a field insulating film in a region where a MOS transistor having a relatively thin gate insulating film is formed with a relatively thick gate insulating film, a channel region of the MOS transistor having the relatively thin gate insulating film is set apart from an inversion-preventing diffusion layer formed under the field insulating film so as not to be influenced by film thickness fluctuation of the field insulating film, etching fluctuation of the relatively thick gate insulating film, and impurity concentration fluctuation at both sides of the channel due to the inversion-preventing diffusion layer.
Claims6
A manufacturing method for a semiconductor device, in which a first MOS transistor having a relatively thick gate insulating film and a second MOS transistor having a relatively thin gate insulating film are formed simultaneously,
- the manufacturing method comprising:
- forming a pad oxide film on a semiconductor substrate of a first conductivity type;
- forming a nitride film on the pad oxide film;
- etching a predetermined region of the nitride film;
- performing ion implantation of impurities into the semiconductor substrate for later forming an inversion-preventing diffusion layer of the first conductivity type and an offset diffusion layer of a second conductivity type, through an opening region in the nitride film formed by the etching;
- forming a field insulating film in the opening region where the nitride film is etched and forming the inversion-preventing diffusion layer of the first conductivity type and the offset diffusion layer of the second conductivity type;
- removing the nitride film and the pad oxide film;
- forming the relatively thick gate insulating film in contact with an active surface region of the semiconductor substrate;
- removing the relatively thick gate insulating film from a source region and a drain region of the active surface region of the first MOS transistor and from an inner portion of the active surface region of the second MOS transistor that is spaced apart from a bird's beak portion of the field insulating film and leaving remaining portions of the relatively thick gate insulating film on the active surface region of the second MOS transistor;
- forming the relatively thin gate insulating film on the remaining portions of the relatively thick gate insulating film and in contact with the active surface region;
- depositing a polycrystalline silicon film on the relatively thick gate insulating film and the relatively thin gate insulating film;
- imparting electrical conductivity to the polycrystalline silicon film;
- etching the polycrystalline silicon film to form a gate electrode,
- wherein the gate electrode is spaced away from the remaining portions of the relatively thick gate insulating film on a second active surface region;
- and
- performing, in a self-aligned manner, ion implantation of impurities into a region which becomes a high concentration diffusion layer of the second conductivity type using the relatively thick gate insulating film as a mask.
A method for simultaneously fabricating high voltage and low voltage transistors in a semiconductor device, the method comprising:
- forming a field isolation region in a semiconductor substrate, the field isolation region defining first and second active surface regions in the semiconductor substrate;
- forming a relatively thick gate insulating film in contact with the field isolation region and the first and second active surface regions;
- removing the relatively thick gate insulating film from a source region and a drain region of the first active region and from an inner portion of the second active region that is spaced apart from a bird's beak portion of the field insulating film and leaving remaining portions of the relatively thick gate insulating film on the first active region and on an edge portion of the second active surface region;
- forming a relatively thin gate insulating film on the remaining portions of the relatively thick gate insulating film and in contact with the first and second active regions;
- depositing a polycrystalline silicon film on the relatively thick gate insulating film and the relatively thin gate insulating film and etching the polycrystalline silicon film to form a gate electrode,
- wherein the gate electrode is spaced away from the remaining portions of the relatively thick gate insulating film on the second active surface region;
- and
- ion implanting impurities to form source/drain diffusion layers of a second conductivity type in the second active surface region using the remaining portions of the relatively thick gate insulating film and the gate electrode as an implant mask.
Dependencies are inferred from the claim text.