Method of manufacturing semiconductor device with offset sidewall structure

A method of manufacturing a semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor substrate and having a thicker gate insulating film than the first n-type MISFET, and a second p-type MISFET formed in a fourth region of the semiconductor substrate and having a thicker gate insulating film than the first p-type MISFET, comprising steps of:

• (a) forming a gate insulating film of the first n-type MISFET over the first region, and forming a gate insulating film of the first p-type MISFET over the second region;
• (b) forming a first gate electrode over the gate insulating film of the first n-type MISFET, and forming a second gate electrode over the gate insulating film of the first p-type MISFET;
• (c) after the step (b), forming first insulating films over side surfaces of the first gate electrode and over side surfaces of the second gate electrode;
• (d) after the step (c), etching the first insulating films such that the first insulating films are kept on side surfaces of the first and second gate electrodes, and such that surfaces of the first and second regions are exposed;
• (e) after the step (d), forming epitaxial layers on the exposed surfaces of the first and second regions;
• (f) after the step (e), under a condition which a first resist pattern covers the second region, forming first n-type impurity regions in the first region by ion implantation method;
• (g) after the step (f), forming second insulating films over the side surfaces of the first gate electrode via the first insulating films and over the side surfaces of the second gate electrode via the first insulating films;
• (h) after the step (g), under a condition which a second resist pattern covers the first region, forming first p-type impurity regions in the second region by ion implantation method;
• (i) after the step (g), forming third insulating films over the side surfaces of the first gate electrode via the first and second insulating films, and over the side surfaces of the second gate electrode via the first and second insulating films, wherein a thickness of each the third insulating film is thicker than a thickness of each the first insulating film and each the second insulating film;
• (j) after the step (i), under a condition which a third resist pattern covers the second region, forming second n-type impurity regions in the first region by ion implantation method, wherein an impurity concentration of each the second n-type impurity region is higher than an impurity concentration of each the first n-type impurity region;
• and
• (k) after the step (i), under a condition which a fourth resist pattern covers the first region, forming second p-type impurity regions in the second region by ion implantation method, wherein an impurity concentration of each the second p-type impurity region is higher than an impurity concentration of each the first p-type impurity region.