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US 8,526,147 B2Granted
High voltage tolerant SCR clamp with avalanche diode triggering circuit
AssigneeNational Semiconductor Corporation
InventorsAntonio Gallerano, Vladislav Vashchenko
Life of this patent
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Abstract
In an LVTSCR, an avalanche diode based control circuit controls both the base of the internal PNP of the LVTSCR as well as the gate of the LVTSCR.
Claims10
A triggering circuit for an SCR ESD protection device that includes a gate and defines a PNP structure with a base region, and is operable to protect a protected circuit, comprising
- an avalanche diode with breakdown voltage above the normal operating voltage of the protected circuit,
- a first reference voltage node operable to control the voltage on the base region of the PNP structure, and
- a second reference voltage node operable to control the voltage on the gate of the SCR ESD protection device,
- wherein the avalanche diode is connected in series with a first resistor between a high voltage pad and ground and the first reference voltage node is defined between the avalanche diode and the resistor,
- further comprising a transistor that includes an anode, a cathode and a control electrode, wherein the first reference voltage node is connected to the control electrode,
- wherein the transistor comprises an NMOS transistor connected in series with a current path transistor that is connected to the high voltage pad,
- wherein the current path transistor comprises a first PMOS transistor connected with its drain to the drain of the NMOS transistor,
- wherein the gate of the first PMOS transistor is biased to keep the first PMOS transistor on during normal operation,
- wherein the gate of the first PMOS transistor is connected to the first reference voltage node through a second PMOS transistor that is connected with its source to the gate of the first PMOS transistor and with its drain to a reference voltage.
6 more elements
A method of reducing the triggering voltage of an L VTSCR that includes a gate and defines a PNP structure with a base, comprising
- increasing the voltage on the gate and decreasing the voltage on the base of the PNP structure during an ESD event,
- wherein increasing the voltage on the gate comprises connecting the gate to a first reference voltage node defined by the anode of an avalanche diode connected to a high voltage pad,
- wherein decreasing the voltage on the base of the PNP structure comprises defining a second reference voltage node defined by a first PMOS transistor connected between the high voltage pad and the drain of an NMOS transistor, the gate of the PMOS transistor being connected to the first reference voltage via a second PMOS transistor.
An ESD protection circuit comprising
- an LVTSCR that includes a gate and defines a PNP structure with a base, an avalanche diode with breakdown voltage above the normal operating voltage of the protected circuit to define a first reference voltage node that is connected to one of the gate of the LVTSCR or the base of the PNP structure, and
- a transistor having a control electrode connected to the first reference voltage node and defining a second reference voltage node relative to a pad or ground, which is connected to the other of the gate of the LVTSCR or the base of the PNP structure,
- wherein the avalanche diode is connected as a high voltage reference by having its cathode connected to the pad and its anode connected to ground via a first resistor, and the transistor is an NMOS transistor connected with its drain to a first PMOS transistor, the gate of the first PMOS transistor being biased to keep the PMOS transistor on during normal operation,
- wherein the biasing is done by connecting the gate of the first PMOS transistor to the first reference voltage node through a second PMOS transistor that is connected with its source to the gate of the first PMOS transistor and with its drain to a reference voltage.
1 more element
Dependencies are inferred from the claim text.