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AssigneePanasonic Corporation
InventorsTakashi Ando, Keiichi Kusumoto, Kenji Shimazaki, Kazuyuki Nakanishi, Tetsurou Toubou
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A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W2 larger than a cell width of cell A-1, but gate length L1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L2. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts
Comprising field effect technology: cMOS gate arrays
Microarchitecture: relative P to N transistor sizes
Inorganic electric semiconductor devices
About 5 years 9 months of term left · ends 30 Jul 2032 (estimated)
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device, and particularly relates to a semiconductor integrated circuit device that is formed by a layout design using a standard cell system.
2. Description of the Related Art
FIG. 1A is a plan view showing a layout example of a standard cell to be used in a semiconductor integrated circuit device according to a first exemplary embodiment;
FIG. 1B is a plan view showing a layout example of a standard cell to be used in a semiconductor integrated circuit device according to the first exemplary embodiment;
FIG. 1C is a plan view showing a layout example of a standard cell to be used in a semiconductor integrated circuit device according to the first exemplary embodiment;
Preferred exemplary embodiments of the present invention are described below with reference to the drawings.
FIGS. 1A, 1B, and 1C are plan views showing layout examples of a standard cell to be used in a semiconductor integrated circuit device according to a first exemplary embodiment. Cell A-1 in FIG. 1A, cell B-1 in FIG. 1B, and cell C-1 in FIG. 1C are all standard cells of the same logic, and show examples of a two-input NAND cell in this case.
In FIGS. 1A, 1B, and 1C, 11 denotes a gate of a MOS transistor, 12 denotes a contact, 13 denotes a P-type diffusion region, 14 denotes an N-type diffusion region, 15 denotes a first layer metal, 16 denotes a via that connects between the first layer metal and a second layer metal, 17 denotes the second layer metal, and 18 denotes an N-well region. Contact 12 connects between the gate or a diffusion layer and the first layer metal. As circuit elements, 21 denotes a power source line to which a power source potential is supplied, 22 denotes a ground line, 23 denotes a terminal wiring that becomes an input terminal (IN1), 24 denotes a terminal wiring that becomes an input terminal (IN2), and 25 denotes a terminal wiring that becomes an output terminal (OUT). Power source line 21 and ground line 22 are formed on first layer metal 15, and terminal wirings 23, 24, and 25 are formed on second layer metal 17. CL denotes a cell frame.