US 8,525,301 B1Granted

Method and apparatus for fabricating heterojunction bipolar transistors with simultaneous low base resistance and short base transit time

AssigneeHRL Laboratories, LLC

InventorTahir Hussain

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Abstract

A method for fabricating heterojunction bipolar transistors that exhibit simultaneous low base resistance and short base transit times, which translate into semiconductor devices with low power consumption and fast switching times, is presented. The method comprises acts for fabricating a set of extrinsic layers by depositing a highly-doped p+ layer on a substrate, depositing a masking layer on highly-doped p+ layer, patterning the masking layer with a masking opening, removing a portion of the highly-doped p+ layer and the substrate through the masking opening in the masking layer to form a well, and growing an intrinsic layered device in the well by a combination of insitu etching and epitaxial regrowth, where an intrinsic layer has a thickness selected independently from a thickness of its corresponding extrinsic layer, thus allowing the resulting device to have thick extrinsic base layer (low base resistance) and thin intrinsic base layer (short base transit times) simultaneously.

Claims19

Dependent claims

A semiconductor device fabricated by a method that comprises acts of:

depositing a set of extrinsic layers on a substrate;
removing a portion of the extrinsic layers and substrate to create a well having an intrinsic portion and an extrinsic portion, where the intrinsic portion is configured for receiving a layered intrinsic semiconductor device, and wherein in removing the portion of the extrinsic layers and substrate to create the well, the well is created to have vertically, outwardly tapering walls;
and
forming a layered intrinsic semiconductor device in the intrinsic portion of the well, wherein the layered intrinsic semiconductor device includes a type of layer selected from a group comprising an intrinsic collector layer, an intrinsic base layer, and an intrinsic sub-collector layer, and wherein in forming the layered intrinsic semiconductor device, at least one of the intrinsic collector layer, intrinsic base layer, and intrinsic sub-collector layer is formed to having vertically, outwardly tapering walls, and where the extrinsic layers include a type of layer selected from a group comprising an extrinsic collector layer, an extrinsic base layer, and an extrinsic sub-collector layer, such that a type of layer of the intrinsic semiconductor device is connected to a same type of layer of the extrinsic layers, and wherein the intrinsic base layer has a thickness that is different than a thickness of the extrinsic base layer.

1 more element

A semiconductor device comprising:

a set of extrinsic layers formed on a substrate;
a well formed in the extrinsic layers and the substrate, the well having an intrinsic portion and an extrinsic portion, and wherein the well is formed to have vertically, outwardly tapering walls;
and
a layered intrinsic semiconductor device in the intrinsic portion of the well, wherein the layered intrinsic semiconductor device includes a type of layer selected from a group comprising an intrinsic collector layer, an intrinsic base layer, and an intrinsic sub-collector layer, and wherein at least one of the intrinsic collector layer, intrinsic base layer, and intrinsic sub-collector layer is formed to having vertically, outwardly tapering walls, and where the extrinsic layers include a type of layer selected from a group comprising an extrinsic collector layer, an extrinsic base layer, and an extrinsic sub-collector layer, such that a type of layer of the intrinsic semiconductor device is connected to a same type of layer of the extrinsic layers, and wherein the intrinsic base layer has a thickness that is different than a thickness of the extrinsic base layer.

1 more element

Dependencies are inferred from the claim text.