Structure including voltage controlled negative resistance
AssigneeInternational Business Machines Corporation
InventorsFen Chen, Elbert E. Huang, Michael A. Shinosky
Life of this patent
Estimating the term…
Abstract
Aspects of the invention provide a semiconductor tunneling device including voltage controlled negative resistance. In one embodiment, the semiconductor tunneling device includes: at least one pair of spaced apart terminals; an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals; and a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.
Claims20
A semiconductor tunneling device, comprising:
- at least one pair of spaced apart terminals;
- an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals;
- and
- a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.
A semiconductor tunneling device, comprising:
- at least one pair of spaced apart copper terminals;
- an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals;
- and
- a hydrogen doped silicon carbide capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.
A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising:
- at least one pair of spaced apart copper terminals;
- an inter-level dielectric (ILD) layer between the at least one pair of spaced apart terminals;
- and
- a dielectric capping layer extending continuously over the at least one pair of spaced apart terminals and the ILD layer.
Dependencies are inferred from the claim text.