Semiconductor fuse with enhanced post-programming resistance
AssigneeGlobalfoundries Inc.
InventorsAndreas Kurz, Maciej Wiatr
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Abstract
Post programming resistance of a semiconductor fuse is enhanced by using an implantation to form an amorphous silicon layer and to break up an underlying high-κ/metal gate. Embodiments include forming a shallow trench isolation (STI) region in a silicon substrate, forming a high-κ dielectric layer on the STI region, forming a metal gate on the high-κ dielectric layer, forming a polysilicon layer over the metal gate, performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate, and forming a silicide on the amorphous silicon layer. By breaking up the metal gate, electrical connection of the fuse contacts through the metal gate is eliminated.
Claims9
A method comprising:
- forming a shallow trench isolation (STI) region in a silicon substrate;
- forming a high-κ dielectric layer on the STI region;
- forming a metal gate on the high-κ dielectric layer;
- forming a polysilicon layer over the metal gate;
- performing an implantation to convert the polysilicon layer into an amorphous silicon layer, wherein the implantation breaks up the metal gate;
- and
- forming a silicide on the amorphous silicon layer.
Dependencies are inferred from the claim text.