Back to results
US 8,524,553 B2Granted
Integrated circuit modification using well implants
AssigneeHRL Laboratories, LLC
InventorsLap-Wai Chow, William M. Clark, Jr., James P Baukus, Gavin J. Harbison
Life of this patent
Estimating the term…
Abstract
A technique for and structures for camouflaging an integrated circuit structure. The integrated circuit structure is formed having a well of a first conductivity type under the gate region being disposed adjacent to active regions of a first conductivity type. The well forming an electrical path between the active regions regardless of any reasonable voltage applied to the integrated circuit structure.
Claims13
A method of camouflaging a circuit comprising the steps of:
- fabricating a device having a gate disposed on an insulating layer, the insulating layer being disposed on a substrate of a first conductivity type, said device having at least two active regions of a second conductivity type;
- and
- inserting a first well in said substrate beneath said gate, said first well beneath said gate having a second conductivity type, said first well beneath said gate being in physical contact with said at least two active regions, said first well beneath said gate providing an electrical path between said at least two active regions regardless of any reasonable voltage applied to said gate.
A method of forming a CMOS circuit comprising the steps of:
- modifying a conventional CMOS double well manufacturing process, wherein a conventional well of a first conductivity type is replaced with a well of a second conductivity type to thereby render a device formed at least in part by said well of a second conductivity permanently ON regardless of any reasonable voltages applied to said device.
Dependencies are inferred from the claim text.