Fin-type field effect transistor
AssigneeInternational Business Machines Corporation
InventorEdward J. Nowak
Life of this patent
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Abstract
Disclosed herein are improved fin-type field effect transistor (FinFET) structures and the associated methods of manufacturing the structures. In one embodiment FinFET drive current is optimized by configuring the FinFET asymmetrically to decrease fin resistance between the gate and the source region and to decrease capacitance between the gate and the drain region. In another embodiment device destruction at high voltages is prevented by ballasting the FinFET. Specifically, resistance is optimized in the fin between the gate and both the source and drain regions (e.g., by increasing fin length, by blocking source/drain implant from the fin, and by blocking silicide formation on the top surface of the fin) so that the FinFET is operable at a predetermined maximum voltage.
Claims20
A method of manufacturing a fin-type field effect transistor, said method comprising:
- etching a semiconductor layer to form, on a top surface of an insulator layer, source region, a drain region parallel to said source region, and a semiconductor fin that extends laterally from said source region to said drain region;
- forming a gate conductor adjacent said semiconductor fin between said source region and said drain region;
- and
- adjusting dimensions of said semiconductor fin between said gate conductor and said source region and between said gate conductor and said drain region in order to optimize resistance so that said transistor is operable at a predetermined maximum voltage,
- said adjusting of said dimensions being performed by design such that said fin-type field effect transistor is asymmetric and such that a first resistance of a first portion of said semiconductor fin between said source region and said gate conductor is less than a second resistance of a second portion of said semiconductor fin between said gate conductor and said drain region.
A method of manufacturing a fin-type field effect transistor, said method comprising:
- etching a semiconductor layer to form, on a top surface of an insulator layer, a source region, a drain region parallel to said source region, and a semiconductor fin that extends laterally from said source region to said drain region;
- forming a gate conductor adjacent said semiconductor fin between said source region and said drain region;
- and
- adjusting dimensions of said semiconductor fin between said gate conductor and said source region and between said gate conductor and said drain region in order to optimize resistance so that said transistor is operable at a predetermined maximum voltage,
- said adjusting of said dimensions being performed by design such that said fin-type field effect transistor is asymmetric, such that a first resistance of a first portion of said semiconductor fin between said source region and said gate conductor is less than a second resistance of a second portion of said semiconductor fin between said gate conductor and said drain region and such that a first capacitance between said source region and said gate conductor is greater than a second capacitance between said gate conductor and said drain region.
A method of manufacturing a fin-type field effect transistor, said method comprising:
- etching a semiconductor layer to form, on a top surface of an insulator layer, a source region, a drain region parallel to said source region, and a semiconductor fin that extends laterally from said source region to said drain region;
- forming a gate conductor adjacent said semiconductor fin between said source region and said drain region;
- and
- adjusting dimensions of said semiconductor fin between said gate conductor and said source region and between said gate conductor and said drain region in order to optimize resistance so that said transistor is operable at a predetermined maximum voltage,
- said adjusting of said dimensions being performed by design such that said fin-type-field effect transistor is asymmetric, such that outer sections of said semiconductor fin that are adjacent to said source region and said drain region are wider than inner sections of said semiconductor fin that are between said outer sections and said gate conductor, such that a first resistance of a first portion of said semiconductor fin between said source region and said gate conductor is less than a second resistance of a second portion of said semiconductor fin between said gate conductor and said drain region and such that a first capacitance between said source region and said gate conductor is greater than a second capacitance between said gate conductor and said drain region.
Dependencies are inferred from the claim text.