Latch structure, frequency divider, and methods for operating same

A method of operating a frequency divider having a plurality of latches, the method comprising:

• driving a first latch of the plurality of latches with a clock signal and a feedback input from a last latch of the plurality of latches;
• selectively switching state of the first latch on both rising and falling edges of the clock signal based on the feedback input;
• driving one or more subsequent latches of the plurality of latches with the clock signal and an output signal from a previous latch to the one or more subsequent latches;
• selectively switching state of the one or more subsequent latches on both rising and falling edges of the clock signal based on the output signal driving the subsequent latches;
• driving the last latch of the plurality of latches with the clock signal and the output signal from the previous latch to the last latch;
• selectively switching state of the last latch on both rising and falling edges of the clock signal based on the output signal from the previous latch to the last latch, wherein the last latch outputs the feedback input;
• and
• wherein operation of each of the plurality of latches comprises:
• providing a high impedance at a first output;
• providing the high impedance at a second output;
• and
• maintaining logic levels of the first and second outputs when a first input and a first clock phase are at different input logic levels and a second input and a second clock phase are at different input logic levels.

A frequency divider having a plurality of latches, the frequency divider comprising:

• means for driving a first latch of the plurality of latches with a clock signal and a feedback input from a last latch of the plurality of latches;
• means for selectively switching state of the first latch on both rising and falling edges of the clock signal based on the feedback input;
• means for driving one or more subsequent latches of the plurality of latches with the clock signal and an output signal from a previous latch to the one or more subsequent latches;
• means for selectively switching state of the one or more subsequent latches on both rising and falling edges of the clock signal based on the output signal driving the subsequent latches;
• means for driving the last latch of the plurality of latches with the clock signal and the output signal from the previous latch to the last latch;
• means for selectively switching state of the last latch on both rising and falling edges of the clock signal based on the output signal from the previous latch to the last latch, wherein the last latch outputs the feedback input;
• and
• wherein operation of each of the plurality of latches comprises:
• means for providing a high impedance at a first output;
• means for providing the high impedance at a second output;
• and
• means for maintaining logic levels of the first and second outputs when a first input and a first clock phase are at different input logic levels and a second input and a second clock phase are at different input logic levels.