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US 8,508,987 B2Granted
Semiconductor device
AssigneeRenesas Electronics Corporation
InventorsTakaharu Tsuji, Genta Watanabe
Life of this patent
Estimating the term…
Abstract
A write disturbance margin of reference cells that generate reference current during read is improved. A bit line forms a clad interconnect structure in the normal cell region where normal cells are disposed, and a partially clad or non-clad interconnect structure in the reference cell region where a reference cell is disposed. Thus, a writing magnetic field intensity applied to the reference cell is smaller than the write magnetic field intensity applied to a normal memory cell during identical write currents.
Claims12
A semiconductor device comprising:
- a memory cell array having a plurality of normal magnetic memory cells disposed in rows and columns, and a plurality of reference cells aligned with said normal magnetic memory cells in a direction of one of a row of the normal magnetic memory cells and a column of the normal magnetic memory cells for generating a reference current in reading data from the normal magnetic memory cell;
- and
- a plurality of first writing magnetic field supply lines arranged corresponding to one of said rows and said columns of the normal magnetic memory cells, and inducing and applying, in data writing, a data writing magnetic field by a current to corresponding ones of the normal magnetic memory cells and the reference cells, each said first writing magnetic field supply line having a clad interconnect structure for said normal magnetic memory cells other than the reference cell of one of a corresponding one of the row and the column and a partially clad or unclad interconnect structure for the reference cell of said corresponding one, said clad interconnect structure being a structure in which a conductor is covered with a high permeability film except a surface of said conductor facing corresponding normal cells, said partially clad or unclad interconnect structure being a structure in which a surface of said conductor facing corresponding reference cell and at least one additional surface of said conductor are non-covered with said high permeability film.
A semiconductor device comprising:
- a plurality of magnetic memory cells disposed in rows and columns and including magnetoresistive elements, respectively, each magnetic resistive element having a layered structure including a free layer having a direction of magnetization set in accordance with data stored to an associated memory cell and a fixed layer having a direction of magnetization fixed regardless of data stored to said associated cell;
- a plurality of first write current lines, each arranged corresponding to one of a row of the memory cells and a column of the memory cells, for applying a current induced magnetic field to corresponding magnetic memory cells in data writing;
- and
- a plurality of second write current lines, each arranged the other of the row of the memory cells and the column of the memory cells, for applying a current induced magnetic field to corresponding magnetic memory cells in the data writing,
- said plurality of first write current lines and said plurality of second write current lines at their respective crossings sandwiching corresponding magnetoresistive elements in between vertically,
- said plurality of magnetic memory cells including a normal magnetic memory cell and a reference magnetic memory cell for generating a reference value for determining data in reading data from said normal magnetic memory cell,
- said crossings including a first crossing sandwiching the magnetoresistive element of said reference magnetic memory cell and a second crossing sandwiching the magnetoresistive element of said normal magnetic memory cell, a conductor constructing an associated one of the first and second write current lines being covered with a magnetic shield film over a smaller surface area at the first crossing than at said second crossing.
4 more elements
Dependencies are inferred from the claim text.