Mask read-only memory having a fake select transistor

A mask read-only memory (ROM) comprising:

• a plurality of doping lines of a second conductivity type formed in a substrate of a first conductivity type and spaced apart from each other in parallel;
• a first insulation film formed on the doping lines and the substrate;
• a plurality of conductive pads formed on the first insulation film;
• a second insulation film formed on the first insulation film and the conductive pads;
• a plurality of wires formed on the second insulation film, spaced apart from each other in parallel, and extending perpendicular to the doping lines;
• second decoders connected to one end of each of the plurality of wires, wherein some of the second decoders are formed of a pass transistor, and at least one of the second decoders is formed of a fake pass transistor;
• a plurality of contact plugs formed in the first insulation film and electrically connecting some but not all of the doping lines to some, but not all of the conductive pads;
• and
• a plurality of vias formed in the second insulation film and electrically connecting some, but not all of the conductive pads to some, but not all of the wires,
• wherein crossings of the doping lines and the wires define memory cells, wherein the contact plugs and the vias are formed in memory cells of a first type, and wherein at least one of the contact plug and the via are missing from memory cells of a second type.

A mask ROM comprising:

• a plurality of doping lines of a second conductivity type formed in a substrate of a first conductivity type and spaced apart from each other in parallel;
• first and second insulation films sequentially formed on the second conductivity type doping lines and the substrate;
• a plurality of wires formed on the second insulation film, spaced apart from each other in parallel, and extending perpendicular to the doping lines;
• a plurality of conductive pads formed on the first insulation film to correspond to crossings of the doping lines and the wires,
• wherein the crossings of the doping lines and the wires define memory cells, wherein memory cells of a first type have the doping lines electrically connected to the wires, and memory cells of a second type have the doping lines electrically disconnected from the wires, wherein the electrical connections comprise a connection between the doping lines and the conductive pads and a connection between the conductive pads and the wires, and
• first decoders connected to one end of the plurality of doping lines, wherein some of the first decoders are formed of select transistors and at least one of the first decoders is formed of a fake select transistor.