Multilayer semiconductor devices with channel patterns having a graded grain structure
AssigneeSamsung Electronics Co., Ltd.
InventorsYong-Hoon Son, Myoungbum Lee, Kihyun Hwang
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Abstract
Memory devices include a stack of interleaved conductive patterns and insulating patterns disposed on a substrate. A semiconductor pattern passes through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate. The graded grain size distribution may be achieved, for example, by partial laser annealing.
Claims12
A memory device comprising:
- a stack of interleaved conductive patterns and insulating patterns disposed on a substrate;
- and
- a semiconductor pattern passing through the stack of conductive patterns and insulating patterns to contact the substrate, the semiconductor pattern having a graded grain size distribution wherein a mean grain size in a first portion of the semiconductor pattern proximate the substrate is less than a mean grain size in a second portion of the semiconductor pattern further removed from the substrate.
A memory device comprising:
- a ground select line pattern on a substrate;
- a stack of interleaved word line patterns and insulating patterns disposed on the ground select line pattern;
- and
- a semiconductor pattern passing through the gate patterns, the insulating patterns and the ground select line pattern to contact the substrate, the semiconductor pattern having a first portion disposed laterally adjacent the ground select line pattern and having a first mean grain size and a second portion laterally adjacent the word line patterns and having a second mean grain size greater than a the first mean grain size.
Dependencies are inferred from the claim text.