BEOL anti-fuse structures for gate last semiconductor devices

A method comprising:

• forming a first metallization layer on an insulating layer, the first metallization layer including, in a substantially axial plane, a first portion of a first electrode of an anti-fuse structure;
• and
• a second electrode about the first portion of the first electrode, but separated therefrom;
• forming, in the substantially axial plane, a dielectric material surrounding the first portion of the first electrode, between the first portion of the first electrode and the second electrode;
• forming an interlayer dielectric (ILD) over the first metallization layer;
• forming at least one via through the ILD over the first portion of the first electrode;
• and
• forming a second metallization layer over the ILD, the second metallization layer including a second portion of the first electrode over the at least one via, wherein the at least one via electrically connects the first and second portions of the first electrode,
• wherein breakdown of a anti-fuse material is configured to enable an operating current to flow between the second electrode and the first electrode in a programmed state of the anti-fuse structure.