US 8,478,022 B2Granted

Failure analysis method, apparatus, and program for semiconductor integrated circuit

AssigneeRenesas Electronics Corporation

InventorMasafumi Nikaido

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Abstract

A failure analysis method for a semiconductor integrated circuit includes deriving a coordinate in a device coordinate system in analysis data for abnormal signal data included in the analysis data of a semiconductor integrated circuit, deriving a correspondence between a coordinate in the device coordinate system and a coordinate in a design coordinate system in design data of the semiconductor integrated circuit for a plurality of reference points in the semiconductor integrated circuit, deriving a coordinate conversion formula between the device coordinate system and the design coordinate system, deriving a position error between a coordinate in the device coordinate system converted by the coordinate conversion formula and a coordinate in the design coordinate system, and extracting a circuit related to an abnormal signal in the design data based on coordinates of the abnormal signal in the device coordinate system using the coordinate conversion formula and the position error.

Claims18

Dependent claims

A failure analysis method, for a semiconductor integrated circuit, said method comprising:

deriving a coordinate in a device coordinate system in analysis data for abnormal signal data included in analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus;
deriving a correspondence between a coordinate in said device coordinate system and a coordinate in a design coordinate system in design data of said semiconductor integrated circuit for a plurality of reference points in said semiconductor integrated circuit;
deriving a coordinate conversion formula between the device coordinate system and the design coordinate system;
deriving a position error between a coordinate in said device coordinate system converted by said coordinate conversion formula and a coordinate in said design coordinate system;
and
extracting a circuit related to an abnormal signal in said design data based on the coordinates of said abnormal signal in said device coordinate system using said coordinate conversion formula and said position error, and
displaying image data of said analysis data and image data of said design data,
wherein,
said coordinate conversion includes specifying said plurality of reference points,
said extracting a circuit includes a signal coordinate calculation that derives a range of the abnormal signal in said design coordinate system using said coordinate conversion formula and said position error, and
said specifying lets a user input coordinates of said reference points in said device coordinate system and said design coordinate system using the image data of said analysis data and said design data of said semiconductor integrated circuit.

8 more elements

A failure analysis apparatus, for a semiconductor integrated circuit, said apparatus comprising:

a signal detection portion that derives a coordinate in a device coordinate system in analysis data for abnormal signal data included in analysis data of a semiconductor integrated circuit obtained from a semiconductor inspection apparatus;
a coordinate conversion portion that derives a correspondence between a coordinate in said device coordinate system and a coordinate in said design coordinate system in design data of said semiconductor integrated circuit for a plurality of reference points in said semiconductor integrated circuit, and that derives a coordinate conversion formula between the device coordinate system and the design coordinate system;
an error calculation portion that derives a position error between a coordinate in said device coordinate system converted by said coordinate conversion formula and a coordinate in said design coordinate system;
a circuit extraction portion that extracts a circuit related to said abnormal signal in said design data based on coordinates of an abnormal signal in said device coordinate system using said coordinate conversion formula and said position error, and
a display unit that displays image data of said analysis data and image data of said design data,
wherein,
said coordinate conversion portion includes a reference point specifying portion that specifies said plurality of reference points,
said circuit extraction portion includes a signal coordinate calculation portion that derives a range of the abnormal signal in said design coordinate system using said coordinate conversion formula and said position error, and
said reference point specifying portion lets a user input coordinates of said reference points in said device coordinate system and said design coordinate system using the image data of said analysis data and said design data displayed by said display unit.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 12/656,723Filed 16 Feb 2010
Priority: JP 2009-03557618 Feb 2009
Published: US 2010/0241374 A123 Sep 2010
Granted: 2 Jul 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G01R 31/2846
Fault-finding or characterising: using hard- or software simulation or using knowledge-based systems, e.g. expert systems, artificial intelligence…
H10P 74/23
Testing or measuring during manufacture or treatment of wafers, substrates or devices: characterised by multiple measurements, corrections,…
G01R
Measuring electric variables
H10P
Generic processes or apparatus for the manufacture or treatment of devices covered