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US 8,476,973 B2Granted
Switch device and layout design method for switch device
AssigneePanasonic Corporation
InventorHeiji Ikoma
Life of this patent
Estimating the term…
Abstract
A switch device includes a plurality of differential switches formed in a semiconductor substrate. Each of the plurality of differential switches includes first and second differential transistors. The plurality of differential switches are placed in such a manner that the first differential transistors are adjacent to each other and the second differential transistors are adjacent to each other.
Claims17
A switch device, comprising:
- a plurality of differential switches formed in a semiconductor substrate, each of the plurality of differential switches having a first differential transistor and a second differential transistor, wherein:
- in each of the plurality of differential switches,
- one of a source and a drain of the first differential transistor is electrically connected to a first output node, the other one of the source and the drain of the first differential transistor is electrically connected to an input node corresponding to the differential switch, and a first control signal corresponding to the differential switch is supplied to a gate of the first differential transistor,
- one of a source and a drain of the second differential transistor is electrically connected to a second output node, the other one of the source and the drain of the second differential transistor is electrically connected to the input node corresponding to the differential switch, and a second control signal corresponding to the differential switch is supplied to a gate of the second differential transistor,
- all first output nodes of the plurality of differential switches are electrically connected to a common first output terminal and all second output nodes of the plurality of differential switches are electrically connected to a common second output terminal, and
- the plurality of differential switches are placed in the semiconductor substrate in such a manner that the first differential transistors are adjacent to each other and the second differential transistors are adjacent to each other.
3 more elements
A layout design method for designing a layout of a switch device including a plurality of differential switches each having first and second differential transistors, the method comprising steps of:
- (a) placing the plurality of differential switches in such a manner that the first differential transistors are adjacent to each other and the second differential transistors are adjacent to each other;
- (b) placing interconnects in such a manner that, in each of the plurality of differential switches,
- one of a source and a drain of the first differential transistor is electrically connected to a first output node, the other one of the source and the drain of the first differential transistor is electrically connected to an input node corresponding to the differential switch, and a first control signal corresponding to the differential switch is supplied to a gate of the first differential transistor, and
- one of a source and a drain of the second differential transistor is electrically connected to a second output node, the other one of the source and the drain of the second differential transistor is electrically connected to an input node corresponding to the differential switch, and a second control signal corresponding to the differential switch is supplied to a gate of the second differential transistor;
- and
- (c) placing interconnects in such a manner that all first output nodes of the plurality of differential switches are electrically connected to a common first output terminal and all second output nodes of the plurality of differential switches are electrically connected to a common second output terminal.
3 more elements
A switch device, comprising:
- a plurality of differential switches formed in a semiconductor substrate, each of the plurality of differential switches having a first differential transistor and a second differential transistor, wherein
- in each of the plurality of differential switches,
- the first differential transistor is electrically connected to a first output node, and
- the second differential transistor is electrically connected to a second output node,
- all first output nodes of the plurality of differential switches are electrically connected to a common first output terminal and all second output nodes of the plurality of differential switches are electrically connected to a common second output terminal, and
- the plurality of differential switches are placed in the semiconductor substrate in such a manner that the first differential transistors are adjacent to each other and the second differential transistors are adjacent to each other.
3 more elements
Dependencies are inferred from the claim text.