Integrated circuit chip with reduced IR drop
AssigneeMediatek Inc.
InventorsChao-Chun Tu, Shih-Hung Lin, Chih-Chien Huang, Tien-Chang Chang
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Abstract
An integrated circuit chip includes a semiconductor substrate; a first interconnection wire having a first portion and a second portion on the semiconductor substrate, wherein the second portion is separated from the first portion; a second interconnection wire situated under the first interconnection wire; a first conductive via electrically coupling the first portion with the second interconnection wire; a conductive layer situated between the first interconnection wire and the second interconnection wire; and a second conductive via electrically coupling the conductive layer with the second portion.
Claims19
An integrated circuit chip comprising:
- a semiconductor substrate;
- a first interconnection wire having a first portion and a second portion on said semiconductor substrate, wherein said second portion is separated from said first portion;
- a second interconnection wire situated under said first interconnection wire;
- a first conductive via electrically coupling said first portion with said second interconnection wire;
- a conductive layer situated between said first interconnection wire and said second interconnection wire, wherein said conductive layer is line shaped to conform to a pattern of said second portion of said first interconnection wire, and said conductive layer is separated from said second interconnection wire;
- and
- a second conductive via electrically coupling said conductive layer with said second portion.
An integrated circuit chip comprising:
- a semiconductor substrate having thereon a plurality of metal layers;
- a power or ground wire having a first portion and a second portion formed in a topmost layer of said plurality of metal layers, wherein said second portion is separated from said first portion;
- a lower interconnection wire situated under said power or ground wire;
- a first conductive via formed in an inter-metal dielectric (IMD) layer between said power or ground wire and said lower interconnection wire for electrically coupling said first portion with said lower interconnection wire;
- and
- a metal-insulator-metal (MIM) structure formed in said IMD layer being electrically coupling to said second portion through a second conductive via, wherein said MIM structure comprises an upper metal plate, a dummy lower metal plate, and a capacitor dielectric layer interposed between said upper metal plate and said dummy lower metal plate, wherein said dummy lower metal plate is electrically floating, and said dummy lower metal plate is line shaped to conform to a pattern of said second portion of said power or ground wire, and said dummy lower metal plate has a bottom surface exposed in said IMD layer.
Dependencies are inferred from the claim text.