Parasitic PIN device in a BiCMOS process and manufacturing method of the same

A manufacturing method of parasitic PIN device in a BiCMOS process, comprising the following steps:

• step 1:
• forming shallow trenches in a P-type silicon substrate by shallow trench etch process and isolating an active region by the shallow trenches;
• step 2:
• forming N-type pseudo buried layers by N-type pseudo buried layer ion implantation at the bottom of the shallow trenches, the N-type pseudo buried layers forming an N-type region;
• step 3:
• forming shallow trench isolation oxide layers by tilling silicon oxide into the shallow trenches;
• step 4:
• forming an I-type region by N-type collector implantation in the active region;
• step 5:
• conducting thermal annealing to the silicon substrate, enabling the N-type region to extend vertically and laterally into the active region and contact with the I-type region during the annealing process;
• step 6:
• forming a P-type region by forming an intrinsic base epitaxial layer on a surface of the active region and forming an extrinsic base implantation region by P-type extrinsic base region ion implantation into the intrinsic base epitaxial layer, the P-type region being in contact with the I-type region;
• step 7:
• forming deep-hole contacts in the shallow trench isolation oxide layers on the N-type region to pick up the N-type region, and forming a metal contact on the P-type region to pick up the P-type region.