US 8,476,693 B2Granted

Nonvolatile semiconductor memory and method for manufacturing the same

AssigneeKabushiki Kaisha Toshiba

InventorsTakayuki Toba, Tohru Ozaki

Life of this patent

Estimating the term…

Loading patent…

Abstract

In one embodiment, a nonvolatile semiconductor memory includes a memory cell array, a first silicon nitride film and a second silicon nitride film. The memory cell array includes NAND cell units. Each of the NAND cell units has memory cell transistors, a source-side select gate transistor and a drain-side select gate transistor. The source-side select gate transistors is disposed in such a manner as to face each other and the drain-side select gate transistors is disposed in such a manner as to face each other. The first silicon nitride film is present in a region between the source-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate. The second silicon nitride film is formed in a region between the drain-side select gate transistors and is disposed at a position lowest from the upper surface of the semiconductor substrate.

Claims18

Dependent claims

A nonvolatile semiconductor memory, comprising:

a memory cell array including a plurality of NAND cell units, each of NAND cell units having a plurality of memory cell transistors formed on a semiconductor substrate at a predetermined spacing, each of memory cell transistors having a first gate insulating film, a floating gate electrode, a second gate insulating film and a control gate electrode stacked on the semiconductor substrate in the order, each of NAND cell units having a source-side select gate transistor disposed at one end of the plurality of memory cell transistors and a drain-side select gate transistor disposed at the other end of the plurality of memory cell transistors, the source-side select gate transistors of the NAND cell unit being disposed in such a manner as to face each other and interpose a first contact therebetween, and the drain-side select gate transistors of the NAND cell unit being disposed in such a manner as to face each other and interpose a second contact therebetween;
a first silicon nitride film present in a region between the source-side select gate transistors and disposed at a position lowest from the upper surface of the semiconductor substrate;
and
a second silicon nitride film formed in a region between the drain-side select gate transistors and disposed at a position lowest from the upper surface of the semiconductor substrate,
wherein a spacing including the first contact between the source-side select gate transistors is smaller than a spacing including the second contact between the drain-side select gate transistors, and
wherein a distance from the upper surface of the semiconductor substrate to the upper surface of the first silicon nitride film is larger than a distance from the upper surface of the semiconductor substrate to the upper surface of the second silicon nitride film.

3 more elements

A method for manufacturing a nonvolatile semiconductor memory, comprising:

forming gate electrodes of a memory cell transistor, a source-side select gate transistor and a drain-side select gate transistor, respectively on a semiconductor substrate;
forming a sidewall insulating film on side surfaces of the gate electrodes of the source-side select gate transistor and the drain-side select gate transistor, respectively;
forming a stopper film on the gate electrodes, on the sidewall insulating films, on the semiconductor substrate between the source-side select gate transistors and on the semiconductor substrate between the drain-side select gate transistors in such a manner that a minimum distance from the upper surface of the semiconductor substrate to the surface of the stopper film is larger between the source-side select gate transistors than between the drain-side select gate transistors;
removing the stopper film formed between the gate electrodes of the source-side select gate transistors;
forming a first inter-layer insulating film in a region between the gate electrodes of the source-side select gate transistors from which the stopper film is removed, and on the stopper film which remained;
and
forming a source contact hole between the gate electrodes of the source-side select gate transistors and a drain contact hole between the gate electrodes of the drain-side select gate transistors, a spacing including the source contact hole between the source-side select gate transistors being smaller than a spacing including the drain contact hole between the drain-side select gate transistors.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/050,297Filed 17 Mar 2011
Priority: JP P2010-2684811 Dec 2010
Published: US 2012/0139024 A17 Jun 2012
Granted: 2 Jul 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 41/43
Simultaneous manufacture of periphery and memory cells: comprising only one type of peripheral transistor
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates
H10B
Electronic memory devices