Methods of adding pads and one or more interconnect layers to the passivated topside of a wafer including connections to at least a portion of the integrated circuit pads thereon

An apparatus for wafer testing, comprising:

• a wafer having a plurality of integrated circuits with a patterned passivation layer disposed on the integrated circuits, the patterned passivation layer having openings therethrough, an individual opening exposing at least a portion of a corresponding integrated circuit pad;
• a conductive line disposed in a generally horizontal plane over the wafer, the conductive line having a first end and a second end, the conductive line being connected to a corresponding integrated circuit pad toward the first end;
• and
• a conductive contact pad disposed over the passivation layer and being connected to the conductive line toward the second end, the contact pad having a surface area that is greater than a surface area of the corresponding integrated circuit pad,
• wherein at least one of the conductive line and the contact pad is printed and is removable by a solvent that does not substantially remove the integrated circuit pad.

An apparatus for wafer testing, comprising:

• a wafer having a plurality of integrated circuits with a patterned passivation layer disposed on the integrated circuits, the patterned passivation layer having openings therethrough, an individual opening exposing at least a portion of a corresponding integrated circuit pad;
• a first conductive pattern having conductive lines with individual conductive lines having a first end and a second end, an individual conductive line being connected to a corresponding integrated circuit pad toward the first end;
• and
• a second conductive pattern comprising one or more individual contact pads disposed over the passivation layer, an individual contact pad being connected to the corresponding conductive line toward the second end, the individual contact pad having a surface area that is greater than a surface area of the corresponding integrated circuit pad,
• wherein the conductive lines and the contact pads comprise conductive nano-particles and thermoset plastic.