Enhanced wafer test line structure

A semiconductor wafer comprising:

• a die area and a scribe area;
• a first metal layer including a first dummy pad in the scribe area;
• a first dielectric layer overlying the first metal layer;
• and
• a second metal layer overlying the first dielectric layer, the second metal layer including a first interconnect in the die area and a first trench pattern in the scribe area, the first trench pattern overlying and aligned with the first dummy pad.

An integrated circuit device comprising:

• a die area surround by a die seal, and a scribe area outside of the die seal
• a first patterned metal layer including at least a portion of a first dummy pad in the scribe area, wherein the first dummy pad forms a first portion of a first test line structure;
• a first dielectric layer overlying the first metal layer in the scribe area;
• and
• a second patterned metal layer overlying the first dielectric layer, the second patterned metal layer including a first interconnect in the die area and at least a second portion of the first test line structure in the scribe area, the second portion of the first test line structure overlying and aligned with the first portion of the first test line structure that includes first dummy pad.