Method of making a charge trapping non-volatile semiconductor memory device

A method of manufacturing a non-volatile semiconductor memory device, the method comprising:

• forming consecutively a channel insulation layer, a charge trapping layer, a blocking insulation layer, and a gate electrode layer over a semiconductor substrate;
• forming a first opening corresponding to a drain region in the semiconductor substrate and a second opening corresponding to a source region in the semiconductor substrate, the first opening having a first width and the second opening having a second width, the first width being larger than the second width;
• depositing a first dielectric layer;
• etching the first dielectric layer to expose the semiconductor substrate through the first opening but not through the second opening;
• forming a P-N junction at the drain region while no P-N junction is formed at the source region;
• removing the first dielectric layer;
• and
• forming a metal layer over the source region and causing the metal layer to react with the semiconductor substrate to form a metal-semiconductor junction at the source region.