Method of manufacturing super-junction semiconductor device
AssigneeFuji Electric Co., Ltd.
InventorTakayuki Shimatou
Life of this patent
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Abstract
A method of manufacturing a super-junction semiconductor device includes growing an alternating conductivity type layer epitaxially on a heavily doped n-type semiconductor substrate, the alternating conductivity type layer including n-type and p-type semiconductor regions arranged alternately and repeated such that n-type and p-type regions are adjoining each other, and arranged to extend perpendicular to the substrate's major surface. The method includes forming a first trench having a predetermined depth in the surface portion of n-type semiconductor region; forming an n-type thin layer on the inner surface of the first trench; and burying gate electrode in the space surrounded by the n-type thin layer with a gate insulator film interposed between a gate electrode and the n-type thin layer.
Claims18
A method of manufacturing a super-junction semiconductor device, the method comprising:
- growing an alternating conductivity type layer epitaxially on a heavily doped semiconductor substrate of a first conductivity type, the alternating conductivity type layer comprising a first semiconductor regions of the first conductivity type and a second semiconductor region of a second conductivity type, the first and second semiconductor regions extending in perpendicular to a major surface of the semiconductor substrate, the first and second semiconductor regions being arranged alternately and repeatedly in parallel to the major surface of the semiconductor substrate such that the first and second semiconductor regions are adjoining to each other;
- forming a first trench having a predetermined depth in a surface portion of the first semiconductor region;
- forming a thin layer of the first conductivity type on an inner surface of the first trench for forming a second trench surrounded by the thin layer of the first conductivity type;
- and
- burying a gate electrode in the second trench with a gate oxide film interposed between the gate electrode and the second trench.
Dependencies are inferred from the claim text.