Methods of forming a semiconductor device with recessed source/design regions, and a semiconductor device comprising same

A method, comprising:

• forming a gate electrode structure of a NMOS transistor above a surface of a semiconducting substrate;
• forming a first sidewall spacer comprised of silicon dioxide proximate said gate electrode structure;
• after forming said first sidewall spacer, performing a first ion implant process using a N-type dopant to form extension implant regions in said substrate for said NMOS transistor;
• forming a second sidewall spacer proximate said first sidewall spacer;
• after forming said second sidewall spacer, performing at least one etching process to define recessed regions in said substrate;
• and
• after performing said at least one etching process, performing a second ion implant process using a N-type dopant to form source/drain implant regions below said recessed regions of said substrate.

A method of forming a PMOS transistor and a NMOS transistor, said NMOS transistor comprising recessed source/drain regions, the method comprising:

• forming a gate electrode structure for said PMOS transistor and a gate electrode structure for said NMOS transistor above a surface of a semiconducting substrate;
• forming a plurality of cavities in said substrate proximate said gate electrode structure of said PMOS transistor;
• performing an epitaxial deposition process to form raised silicon-germanium regions is said cavities of said PMOS transistor, said raised silicon-germanium regions having an amount of silicon-germanium material positioned above a surface of said semiconducting substrate;
• and
• after forming said raised silicon-germanium regions, performing a common etching process on said PMOS transistor and said NMOS transistor to define recessed regions in said substrate proximate said gate electrode structure of said NMOS transistor and to reduce said amount of said silicon-germanium material positioned above said surface of said substrate for said PMOS transistor.

A method of forming a PMOS transistor and a NMOS transistor, said NMOS transistor comprising recessed source/drain regions, the method comprising:

• forming a gate electrode structure for said PMOS transistor and a gate electrode structure for said NMOS transistor above a surface of a semiconducting substrate;
• performing a first ion implant process using a P-type dopant to form extension implant regions in said substrate for said PMOS transistor;
• after performing said first ion implant process, forming a plurality of cavities in said substrate proximate said gate electrode structure of said PMOS transistor;
• performing an epitaxial deposition process to form raised silicon-germanium regions is said cavities of said PMOS transistor, said raised silicon-germanium regions having an amount of silicon-germanium material positioned above a surface of said semiconducting substrate;
• after forming said raised silicon-germanium regions, performing a second ion implant process using a N-type dopant to form extension implant regions in said substrate for said NMOS transistor;
• after performing said second ion implant process, performing at least one common etching process on said PMOS transistor and said NMOS transistor to define recessed regions in said substrate proximate said gate electrode structure of said NMOS transistor and to reduce said amount of said silicon-germanium material positioned above said surface of said substrate for said PMOS transistor;
• and
• after forming said recessed regions in said substrate proximate said gate electrode of said NMOS transistor, performing at least one additional ion implant process to form source/drain implant regions in said substrate for said PMOS transistor and said NMOS transistor, said source/drain implant regions for said PMOS transistor comprising P-type dopant material, said source/drain regions for said NMOS transistor comprising N-type dopant material and being positioned beneath said recessed regions of said substrate.