Nonvolatile latch circuit and logic circuit, and semiconductor device using the same

A latch circuit comprising:

• a latch portion;
• and
• a data holding portion for holding data of the latch portion,
• the latch portion comprising:
• a first element;
• and
• a second element,
• wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, and
• wherein the input of the first element is electrically connected to a wiring supplied with an input signal, and the output of the first element is electrically connected to a wiring supplied with an output signal,
• the data holding portion comprising:
• a transistor;
• a capacitor;
• and
• an inverter,
• wherein a channel formation region of the transistor includes an oxide semiconductor layer, and
• wherein one of a source electrode and a drain electrode of the transistor is electrically connected to the wiring supplied with the output signal, the other of the source electrode and the drain electrode of the transistor is electrically connected to one of electrodes of the capacitor and an input of the inverter, and an output of the inverter is electrically connected to the wiring supplied with the input signal.

A latch circuit comprising:

• a latch portion;
• and
• a data holding portion for holding data of the latch portion,
• the latch portion comprising:
• a first inverter;
• and
• a second inverter,
• wherein an output of the first inverter is electrically connected to an input of the second inverter, and an output of the second inverter is electrically connected to an input of the first inverter, and
• wherein the input of the first inverter is electrically connected to a wiring supplied with an input signal, and the output of the first inverter is electrically connected to a wiring supplied with an output signal,
• the data holding portion comprising:
• a transistor;
• and
• a third inverter,
• wherein a channel formation region of the transistor includes an oxide semiconductor layer, and
• wherein one of a source electrode and a drain electrode of the transistor is electrically connected to the wiring supplied with the output signal, the other of the source electrode and the drain electrode of the transistor is electrically connected to an input of the third inverter, and an output of the third inverter is electrically connected to the wiring supplied with the input signal.

A latch circuit comprising:

• a latch portion;
• and
• a data holding portion for holding data of the latch portion,
• the latch portion comprising:
• a first inverter;
• and
• a second inverter,
• wherein an output of the first inverter is electrically connected to an input of the second inverter, and an output of the second inverter is electrically connected to an input of the first inverter, and
• wherein the input of the first inverter is electrically connected to a wiring supplied with an input signal, and the output of the first inverter is electrically connected to a wiring supplied with an output signal,
• the data holding portion comprising:
• a transistor;
• a capacitor;
• and
• a third inverter,
• wherein a channel formation region of the transistor includes an oxide semiconductor layer, and
• wherein one of a source electrode and a drain electrode of the transistor is electrically connected to the wiring supplied with the output signal, the other of the source electrode and the drain electrode of the transistor is electrically connected to one of electrodes of the capacitor and an input of the third inverter, and an output of the third inverter is electrically connected to the wiring supplied with the input signal.