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US 8,410,738 B2Granted
Semiconductor device
AssigneeRohm Co., Ltd.
InventorHisashi Sugie
Life of this patent
Estimating the term…
Abstract
Multiple pads are provided to a semiconductor chip of a semiconductor device. A first pad is arranged on a path for a first signal set to a voltage that corresponds to a first level in the active state. The first signal is input to the semiconductor chip from outside the semiconductor device, or is output to outside the semiconductor device from the semiconductor chip. A second pad is provided in order to receive a setting voltage. A first pin is connected to a first pad via a connection member, and receives the first signal from outside the semiconductor device, or from the semiconductor chip via the first pad. A second pin receives, from outside, a second signal set to a voltage that corresponds to the first level or a second level which is the complement of the first level.
Claims25
A semiconductor device comprising:
- a plurality of pins;
- a semiconductor chip having a plurality of pads which allow signals to be input and output, and configured to execute signal processing in one state selected from among a plurality of states according to at least one given setting voltage;
- and
- connection members configured to connect the plurality of pads to corresponding pins,
- wherein the plurality of pads comprises
- a first pad arranged on a path for a first signal which is set to a voltage that corresponds to a first level when the semiconductor device is in an active state, and which is input to the semiconductor chip from outside the semiconductor device, or which is output from the semiconductor chip to outside the semiconductor device, and
- at least one second pad configured to receive the aforementioned at least one setting voltage,
- and wherein the plurality of pins comprises
- a first pin which is connected to the first pad via the connection member, and which is configured to receive the first signal from outside the semiconductor device or from the semiconductor chip via the first pad, and
- a second pin configured to receive a second signal which is set to a voltage that corresponds to the first level or a second level that is the complement of the first level.
7 more elements
A semiconductor device comprising:
- a plurality of pins;
- a semiconductor chip having a plurality of pads which allow signals to be input and output, and configured to execute signal processing in one state selected from among a plurality of states according to at least one given setting voltage;
- and
- connection members configured to connect the plurality of pads to the corresponding pins,
- wherein the plurality of pads comprises
- a first pad arranged on a path for a first signal which is set to a voltage that corresponds to a first level when the semiconductor device is in an active state, and which is input to the semiconductor chip from outside the semiconductor device, or which is output from the semiconductor chip to outside the semiconductor device,
- at least one second pad configured to receive the aforementioned at least one setting voltage, and
- a third pad arranged on a path for a third signal which is set to a voltage that corresponds to a second level when the semiconductor device is in the active state, and which is input to the semiconductor chip from outside the semiconductor device, or which is output from the semiconductor chip to outside the semiconductor device,
- and wherein the plurality of pins comprises
- a first pin which is connected to the first pad via the connection member, and is configured to receive the first signal from outside the semiconductor device or from the semiconductor chip via the first pad, and
- a third pin which is connected to the third pad via the connection member, and is configured to receive the third signal from outside the semiconductor device or from the semiconductor chip via the third pad,
- and wherein the first pad, the aforementioned at least one second pad, and the third pad are arranged adjacently,
- and wherein the first pin and the third pin are arranged adjacently,
- and wherein the first pad is arranged at a position in the vicinity of the first pin,
- and wherein the aforementioned at least one second pad is arranged in the vicinity of the first pad and the third pad,
- and wherein the third pad is arranged at a position in the vicinity of the third pin.
13 more elements
A semiconductor device comprising:
- a plurality of pins;
- a semiconductor chip having a plurality of pads which allow signals to be input and output, and configured to execute signal processing in one state selected from among a plurality of states according to at least one given setting voltage;
- and
- connection members configured to connect the plurality of pads to the corresponding pins,
- wherein the plurality of pads comprises
- a first pad arranged on a path for a first signal which is set to a voltage that corresponds to a first level when the semiconductor device is in an active state, and which is input to the semiconductor chip from outside the semiconductor device, or which is output from the semiconductor chip to outside the semiconductor device, and
- at least one second pad configured to receive the aforementioned at least one setting voltage,
- and wherein the plurality of pins comprises a first pin which is connected to the first pad via the connection member, and which is configured to receive the first signal from outside the semiconductor device or from the semiconductor chip via the first pad,
- and wherein the aforementioned at least one second pad is pulled up or pulled down to a voltage that corresponds to a second level that is the complement of the first level when the semiconductor device is in the active state.
6 more elements
Dependencies are inferred from the claim text.