Loading patent…
AssigneeInstitute of Microelectronics, Chinese Academy of Sciences
InventorsTao Yang, Chao Zhao, Junfong Li
Estimating the term…
A method for improving the within die uniformity of the metal plug CMP process in the gate last route is provided. Before performing the CMP process for forming the metal plug, a metal etching process is applied, so that the step height between the metal layers in the contact hole area and the non-contact hole area is greatly reduced. Therefore, the relatively small step height will exert a significantly less effect on the following CMP process, so that the step height will be limitedly transferred to the top of metal plug after finishing CMP process. In this way, the recess on top of the metal plug is largely reduced, so that a flat top of the metal plug is obtained, and within die uniformity and electrical properties the device are improved.
A method for improving within die uniformity of the metal plug CMP process in the gate last route, comprises:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
From the US filing history. Foreign family members aren’t listed.
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation
Chemomechanical polishing [CMP]: of conductive or resistive materials
By chemical means: by vapour etching only
Generic packages, interconnections, connectors or other constructional details of devices covered by
About 4 years 6 months of term left · ends 20 Apr 2031 (estimated)
This application is a Section 371 National Stage Application of International Application No. PCT/CN2011/000692, filed on Apr. 20, 2011, which claims priority to CN201110005058.1 filed on Jan. 11, 2011 entitled “Method for improving within die uniformity of metal plug chemical mechanical planarization process in gate last route”, the entire contents of which are incorporated herein by reference in their entirety.
The present invention relates to a process method for fabricating a semiconductor device, and more particularly, to a method for improving within die uniformity of metal plug chemical mechanical planarization process in gate last route.
The successful application of the high k/metal gate route in technology nodes of 45 nm makes it a key modular engineering, which is essential for technology nodes below 30 nm. Nowadays, only the Intel Corporation, which persisted in gate last route succeeding in the mass-production at the 45 nm and 32 nm technology nodes. In recent years, the industry giants like Samsung, TMSC, Infineon etc, which follow closely the IBM industrial alliance, also change their R&D focus from gate first to the gate last route.
FIG. 1 an ideal device structure after the W-Al buffer CMP process;
FIG. 2 the step height of the metal layer before a CMP process;
FIG. 3 the metal plug recess after a conventional metal CMP
The features of the technical solutions according to the present invention and the technical effects will be described hereinafter in details with reference to the accompanying drawings and the exemplary embodiment(s).
Firstly, as shown in FIG. 4, in the gate last route, a substrate 1 is provided, on which metal gates 2 and one or more contact holes 3 between the adjacent metal gates 2 are provided. The substrate 1 can be common substrates in the semiconductor device, such as Si, GaAs, etc.; the material for the metal gate 2 includes, but not limited to, Al, and other metals suitable for fabricating the gate may also be used. In general, the height of the metal gate 2 is 1000˜1500 Å.
A metal layer 4 is deposited on the surface of the substrate 1, as shown in FIG. 5. The process like CVD, PVD, ALD, etc. can be applied for depositing the metal layer 4.