Ultra-low drain-source resistance power MOSFET
AssigneeVishay-Silconix
InventorsThe-Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo-In Chen
Life of this patent
Estimating the term…
Abstract
Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent and contiguous to a first epitaxial layer. The first epitaxial layer is formed adjacent and contiguous to a substrate highly doped with red Phosphorous. The novel red Phosphorous doped substrate enables a desirable low drain-source resistance.
Claims7
A semiconductor device comprising:
- a substrate doped with atoms of the set comprising red Phosphorus and Antimony;
- a first epitaxial layer disposed adjacent to said substrate, the first epitaxial layer characterized in that it limits the diffusion of red Phosphorous from the substrate;
- and
- a second epitaxial layer disposed adjacent to said first epitaxial layer for formation of trench metal oxide semiconductor field effect transistors.
A semiconductor device comprising:
- a first epitaxial layer formed on a red Phosphorous and Antimony doped substrate, wherein said first epitaxial layer characterized in that it limits the diffusion of said red Phosphorous from said substrate;
- a second epitaxial layer;
- and a plurality of trench power MOSFETs formed in said second epitaxial layer, and wherein said second epitaxial layer is formed adjacent and contiguous to said first epitaxial layer.
Dependencies are inferred from the claim text.