Gate speed regulator dithering ring oscillator to match critical path circuit
AssigneeWestern Digital Technologies, Inc.
InventorGeorge J. Bennett
Life of this patent
Estimating the term…
Abstract
A computing device is disclosed comprising digital circuitry including a critical path circuit, and a gate speed regulator. A ring oscillator generates an oscillation frequency, and dither circuitry periodically adjusts a number of inverter elements in the ring oscillator in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit. A comparator compares the oscillation frequency to a reference frequency to generate an error signal, and an adjustable circuit, responsive to the error signal, adjusts at least one of a supply voltage and a clocking frequency applied to the digital circuitry.
Claims15
A computing device comprising:
- digital circuitry comprising a critical path circuit;
- and
- a gate speed regulator comprising:
- a ring oscillator operable to generate an oscillation frequency;
- dither circuitry operable to periodically adjust a number of inverter elements in the ring oscillator over a number of cycles in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit;
- a comparator operable to compare the oscillation frequency to a reference frequency to generate an error signal;
- and
- an adjustable circuit, responsive to the error signal, for adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry.
A method of operating a computing device comprising digital circuitry comprising a critical path circuit, the method comprising:
- using a ring oscillator to generate an oscillation frequency;
- periodically adjusting a number of inverter elements in the ring oscillator over a number of cycles in order to adjust an average propagation delay of the ring oscillator relative to a propagation delay of the critical path circuit;
- comparing the oscillation frequency to a reference frequency to generate an error signal;
- and
- adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry in response to the error signal.
Dependencies are inferred from the claim text.