Regulating power consumption of digital circuitry using a multi-layer ring oscillator
AssigneeWestern Digital Technologies, Inc.
InventorGeorge J. Bennett
Life of this patent
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Abstract
A computing device is disclosed comprising digital circuitry fabricated on a multi-layer integrated circuit including a first layer and a second layer, and a multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer. The propagation delay frequency is compared to a reference frequency to generate a frequency error, and at least one of a supply voltage and a clocking frequency applied to the digital circuitry is adjusted in response to the frequency error.
Claims24
A computing device comprising:
- digital circuitry fabricated on a first layer and a second layer of a multi-layer integrated circuit;
- a first multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the first multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer;
- a reference frequency;
- a frequency comparator for generating a frequency error representing a difference between the reference frequency and the propagation delay frequency;
- and
- an adjustable circuit, responsive to the frequency error, for adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry.
A method of operating a computing device comprising digital circuitry fabricated on a first layer and a second layer of a multi-layer integrated circuit, a first multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the first multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer, the method comprising:
- generating a frequency error representing a difference between a reference frequency and the propagation delay frequency;
- and
- adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry in response to the frequency error.
Dependencies are inferred from the claim text.