Programmable buffer

An integrated circuit having a buffer comprising:

• a main driver section having a main driver input node and a main driver output node, the main driver section operable to buffer a data signal received at the input node and provide the buffered data signal at the output node;
• and
• a mixed-mode section connected to the main driver section and selectively configurable responsive to at least one drive control signal to provide any of a plurality of different mixed modes of operation for the buffer,
• wherein in a first mixed mode of operation the peak voltage of the data signal exceeds the supply voltage for the buffer and in a second mixed mode of operation the peak voltage of the data signal is lower than the supply voltage for the buffer.

An integrated circuit having a buffer comprising:

• a main driver section having a main driver input node (e.g., INS_IN) and a main driver output node, the main driver section operable to buffer a data signal received at the input node and provide the buffered data signal at the output node;
• and
• a level-shifting section having an input node at a first voltage domain connected to the main driver output node to receive the buffered data signal and an output node at a second voltage domain different from the first voltage domain to provide the buffered data signal, wherein the level-shifting section comprises:
• level-shifting circuitry having an input node at the first voltage domain and an output node at the second voltage domain;
• and
• look-ahead circuitry connected to the input node of the level-shifting section and connected to a downstream node at the second voltage domain, wherein the look-ahead circuitry speeds up switching of the buffered data signal at the downstream node based on a transition of the buffered data signal at the input node of the level-shifting section.