QC-LDPC code decoder and corresponding decoding method

A QC-LDPC code decoding method, characterized in using means of software hardware accelerator to perform the QC-LDPC code decoding, the method comprising:

• distributing the storage space for a data memory area based on the structure of a QC-LDPC code check matrix and establishing an index for data addressing by a general-purpose processor;
• storing, block by block, the information which is needed for the decoding process by the memory area, the information comprising initial information of the variable nodes, check node information, and variable node information during iteration;
• initializing the data memory area and then performing parity check row block by row block by the general-purpose processor or a hardware accelerator;
• if the check equations of all the row blocks are met, an output decision is made, if not, check node updating is performed row block by row block and variable node updating is conducted column block by column block by the general-purpose processor or the hardware accelerator;
• transmitting the needed information block by block between the general-purpose processor and the hardware accelerator;
• and
• if the maximal iteration number is reached, an output decision is made, if not, the repeating the step of parity check and starting a new round of iteration, and
• wherein, when the hardware accelerator is used to accomplish part of the information processing functions during the decoding process including parity check, check node updating, and variable node updating, the remaining information processing functions are completed by the general-purpose processor.

A QC-LDPC code decoder, comprising:

• a general-purpose processor configured for:
• distributing storage space for data memory area based on the structure of the QC-LDPC code check matrix;
• establishing an index for data addressing;
• controlling the QC-LDPC code decoding process;
• scheduling information processing operations during the decoding process;
• and
• realizing part of the information processing operations during the decoding process including parity check, check node updating, and variable node updating;
• a data memory area configured for storing the information needed for the decoding process block by block, wherein the information includes initial information of the variable nodes, check node information and variable node information during iteration;
• and
• a hardware accelerator configured for conducting all or part of the information processing operations during the decoding process including parity check, check node updating, and variable node updating.